The present disclosure is directed to bit scan technology.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Typically, a program voltage VPGM is applied to the control gate during a program operation as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4V. VPGM can be applied to the control gates of flash memory elements. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of elements being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed. For arrays of multi-state flash memory elements, a verification step may be performed for each state of an element to determine whether the element has reached its data-associated verify level. For example, a multi-state memory element capable of storing data in four states may need to perform verify operations for three compare points.
When programming an EEPROM or flash memory device, such as a NAND flash memory device in a NAND string, typically VPGM is applied to the control gate and the bit line is grounded, causing electrons from the channel of a cell or memory element, e.g., storage element, to be injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element is raised so that the memory element is considered to be in a programmed state.
There is often a need to count the number of logic ‘1’s or ‘0’s in an N-bit string. During a program operation, for example, a page of binary target data may be provided in a first set of data latches of the memory device. A page (e.g., N) of memory cells are then programmed in parallel according to the target data to allow the N memory cells to reach their respective target states. After programming of the page is done, the page of binary data is read back from the group of memory cells and stored in a second set of data latches. The binary data pages of the first and second sets of data latches can be compared to verify that the programming was performed correctly. Typically, an XOR operation is performed bit-by-bit between the two sets, and a ‘1’ indicates a disagreement between the two sets. Thus, the result of the comparison is an N-bit string where any occurrence of ‘1’s would indicate a memory cell that fails to program correctly. Of course, in a reverse logic implementation, ‘0’s instead of ‘1’s could indicate an incorrectly programmed memory cell.
If the number of failed bits exceeds a correction capability of a built-in error correction control (ECC) scheme, the programming may be repeated or re-done. However, in today's generation of flash memory, the data page is typically quite large, as for example, of the order of 10^5 bits. Existing circuits and methods to scan this string for occurrence of “1”s can be time and/or hardware intensive.